Electro-thermal cooling devices and methods of fabrication thereof

ABSTRACT

In one embodiment, a semiconductor module includes a leadframe having a first side and an opposite second side. A semiconductor chip is disposed over the first side of the leadframe. A switching element is disposed under the second side of the leadframe. In another embodiment, a method of forming a semiconductor module includes providing a semiconductor device having a leadframe. A semiconductor chip is disposed over a first side of the leadframe. A switching element is attached at an opposite second side of the leadframe.

TECHNICAL FIELD

The present invention relates generally to electronic devices, and moreparticularly to electro-thermal cooling devices and methods offabrication thereof.

BACKGROUND

Semiconductor devices are used in a variety of electronic and otherapplications. Semiconductor devices comprise integrated circuits ordiscrete devices that are formed on semiconductor wafers by depositingone or more types of thin films of material over the semiconductorwafers, and patterning the thin films of material to form the integratedcircuits.

The semiconductor devices are typically packaged within a ceramic or aplastic body to protect the semiconductor devices from physical damageor corrosion. The packaging also supports the electrical contactsrequired to connect a semiconductor device, also referred to as a die ora chip, to other devices external to the packaging.

Many different types of packaging are available depending on the type ofsemiconductor device and the intended use of the semiconductor devicebeing packaged. Typical packaging features, such as dimensions of thepackage, pin count, etc., may comply with open standards from JointElectron Devices Engineering Council (JEDEC), among others. Packagingmay also be referred as semiconductor device assembly or simplyassembly.

Packaging also supports the thermal cooling requirements of the devices.Conventional packaging may not provide sufficient thermal protectionwhen the semiconductor devices generate large amounts of heat.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the present invention, asemiconductor module includes a leadframe having a first side and anopposite second side. A semiconductor chip is disposed over the firstside of the leadframe. A switching element is disposed under the secondside of the leadframe.

In accordance with an embodiment of the present invention, asemiconductor module comprises a first discrete semiconductor deviceincluding a first lead and a second lead. The semiconductor modulefurther comprises a first switching element having a first terminal anda second terminal. The first terminal of the first switching element iselectrically and thermally coupled to the first discrete semiconductordevice. The first switching element is configured to conduct heat awayfrom the first discrete semiconductor device.

In another embodiment, a method of forming a semiconductor moduleincludes providing a semiconductor device having a leadframe. Asemiconductor chip is disposed over a first side of the leadframe. Aswitching element is attached at an opposite second side of theleadframe.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawing, in which:

FIG. 1, which includes FIGS. 1A-1C, illustrates a conventionalsemiconductor device, wherein FIG. 1A illustrates a projection view,wherein FIG. 1B illustrates a cross-sectional side view of thesemiconductor device, and wherein FIG. 1C illustrates a magnifiedcross-sectional view of the semiconductor device;

FIG. 2, which includes FIGS. 2A-2D, illustrates a semiconductor devicein accordance with an embodiment of the invention, wherein FIG. 2Aillustrates a projection view, wherein FIG. 2B illustrates across-sectional side view of the semiconductor device, wherein FIG. 2Cillustrates a top view of the semiconductor device, and wherein FIG. 2Dillustrates a magnified cross-sectional side view of the semiconductordevice;

FIG. 3, which includes FIGS. 3A-3D, illustrates schematics of electricalequivalent circuit diagram of semiconductor devices in accordance withembodiments of the invention;

FIG. 4, which includes FIGS. 4A and 4B, illustrates cross-sectionalviews of the semiconductor device in accordance with embodiments of theinvention;

FIG. 5, which includes FIGS. 5A and 5B, illustrates cross-sectionalviews of the semiconductor device in which the switching element isdisposed within the encapsulant in accordance with embodiments of theinvention;

FIG. 6, which includes FIGS. 6A and 6B, illustrates cross-sectionalviews of the semiconductor device in which the switching element isdisposed within an auxiliary insulating layer in accordance withembodiments of the invention;

FIG. 7, which includes FIGS. 7A and 7B, illustrates cross-sectionalviews of the semiconductor device in which the switching element isdisposed between a heatsink and the leadframe in accordance withembodiments of the invention;

FIG. 8, which includes FIGS. 8A and 8B, illustrates cross-sectionalviews of the semiconductor device in which the switching element isdisposed within the heatsink in accordance with embodiments of theinvention;

FIG. 9 illustrates a schematic circuit using embodiments of theinvention;

FIG. 10, which includes FIGS. 10A-10D, illustrates a semiconductordevice during various stages of fabrication in accordance with anembodiment of the invention; and

FIG. 11, which includes FIGS. 11A-11C, illustrates a semiconductordevice during various stages of fabrication in accordance with anembodiment of the invention.

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the embodiments andare not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of various embodiments are discussed in detailbelow. It should be appreciated, however, that the present inventionprovides many applicable inventive concepts that can be embodied in awide variety of contexts. The embodiments discussed are merelyillustrative of one way to make and use the invention, and do not limitthe scope of the invention.

Power semiconductor dies have special requirements (e.g., due to thehigh voltages and high heat generation) and require good thermalmanagement. Consequently, packages for power semiconductor devices haveenhanced performance requirements while being very sensitive toproduction costs. As will be described below, various embodiments of thepresent invention enable formation of packages for power semiconductorpackages with improved performance without significantly increasingcosts.

FIG. 1, which includes FIGS. 1A-1C, illustrates a conventionalsemiconductor device, wherein FIG. 1A illustrates a projection view,wherein FIG. 1B illustrates a cross-sectional side view of thesemiconductor device, and wherein FIG. 1C illustrates a magnifiedcross-sectional view of the semiconductor device.

The semiconductor device 10 includes a package 40 having a plurality ofleads 50 or pins extending out of the body of the package 40 along oneside of the package. The plurality of leads 50 may comprise a number ofleads in various embodiments depending on the package type. In oneembodiment, the plurality of leads 50 comprises a gate/base lead 51, adrain/collector lead 52, and a source/emitter lead 53. The package 40includes an opening 30 for securely mounting a heatsink underneath thepackage 40.

Referring to FIG. 1B, which is a sectional view of FIG. 1A, thesemiconductor device 10 comprises a leadframe 60 disposed within aencapsulant 80. The leadframe 60 includes the plurality of leads 50. Afirst semiconductor chip 70 is disposed over a die attach or die paddleof the leadframe 60. The leadframe 60 couples to a first contact regiondisposed on a first side 61 of the first semiconductor chip 70. Theopposite second side 62 of the first semiconductor chip 70 is coveredwith an encapsulant.

The encapsulant 80 has a first portion 80A and a second portion 80B. Thefirst portion 80A is directly over the first semiconductor chip 70 whilethe second portion 80B is laterally adjacent the first semiconductorchip 70. The second portion 80B is directly away from the direction ofthe plurality of leads 50 such that the first semiconductor chip 70 isdisposed between the plurality of leads 50 and the second portion 80B.As illustrated, the first portion 80A is thicker than the second portion80B. An opening 30 is disposed within the encapsulant 80. The opening 30is configured to enable mounting of a heatsink. For example, a heatsinkmay be attached to the semiconductor device 10 using a screw mountedthrough the opening 30.

Referring again to FIG. 1B, the encapsulant 80 includes a first majorsurface 81 for the first portion 80A and the second portion 80B, forexample, for mounting a heatsink. The first major surface 81 is planarto maximize heat dissipation from the first semiconductor chip 70 to theheatsink. The first portion 80A of the encapsulant 80 includes a secondmajor surface 82 disposed over the second side 62 of the firstsemiconductor chip 70.

As illustrated in the magnified cross-sectional view of FIG. 1C, a thinportion of the encapsulant 80 is disposed under the leadframe 60. As thesecond major surface 82 of the encapsulant 80 is mounted tightly withthe heatsink, the thin portion of the encapsulant 80 serves as a thermalconductor while providing electrical isolation between the heatsink andthe leadframe 60. However, even thin layers of the encapsulant 80 havehigh thermal resistance. For example, the first thickness D1 of theencapsulant 80 has a strong correlation with the efficiency of removingthermal energy from the first semiconductor chip 70. Consequently, thismay result in poor heat extraction from the semiconductor devicesdegrading the semiconductor devices. Further, the high sensitivity tothe first thickness D1 of the encapsulant 80 may result in largevariations in heat extraction efficiency between different packages dueto process variations.

A structural embodiment of the invention will be described using FIG. 2.Embodiments of electrical equivalent circuit diagrams of thesemiconductor devices will be described using FIG. 3. Further structuralembodiments of the invention will be described using FIGS. 4-8. Anillustrative converter circuit applying embodiments of the inventionwill be described using FIG. 9. Embodiments of methods of fabricatingthe semiconductor device will be described using FIGS. 10 and 11.

FIG. 2, which includes FIGS. 2A-2D, illustrates a semiconductor devicein accordance with an embodiment of the invention, wherein FIG. 2Aillustrates a projection view, wherein FIG. 2B illustrates across-sectional side view of the semiconductor device, wherein FIG. 2Cillustrates a top view of the semiconductor device, and wherein FIG. 2Dillustrates a magnified cross-sectional side view of the semiconductordevice.

Embodiments of the invention provide electrical isolation withoutcompromising thermal efficiency. Various embodiments of the inventioninclude a switch that changes thermal and/or electrical conductivity.

FIG. 2A illustrates the projection view of the semiconductor device 10,which may be compliant with protocols of standard packages. In oneembodiment, the projection view of the semiconductor device 10 may besimilar to FIG. 1.

FIG. 2B illustrates a first semiconductor chip 70 attached to aleadframe 60 having a plurality of leads 50. Referring to FIG. 2B, invarious embodiments, an switching element 110 is disposed under theleadframe 60. The switching element 110 allows thermal conduction whenheat is being generated at the first semiconductor chip 70. However, theswitching element 110 electrically isolates the leadframe 60 from thepotential on a heatsink attached to the first major surface 81 of theencapsulant 80.

As illustrated, the switching element 110 contacts a bottom surface ofthe leadframe 60. Further, the switching element 110 has a foot print(area) similar to the die paddle of the leadframe 60 to which theelectro-thermal switch is attached. This maximizes the thermalefficiency of heat removal from the first semiconductor chip 70.

The switching element 110 may comprise any suitable type ofthermoelectric device in various embodiments. In one or moreembodiments, the switching element 110 comprises a diode. In oneembodiment, the switching element 110 comprises an inorganicsemiconductor diode such as a silicon p/n junction diode.

In another embodiment, the switching element 110 may comprise a diodeformed from a carbon based material. In one embodiment, the organicdiode may comprise polymer materials, which may operate usingelectrochemical reactions such as redox reactions. The electrochemicalreactions may result in current flow through the polymer material,making the polymer conductive. Examples of carbon based material diodesmay include materials fabricated using polyacetylene,ethylenedioxythiophene, carbon nanotubes, graphene, and others.

In some embodiments, the switching element 110 may comprise a diodebased on organic semiconductor materials and inorganic semiconductormaterials. Embodiments of the invention may also include electro-thermalswitches based on three terminal semiconductor devices. In anotherembodiment, the switching element 110 comprises a heat pump, forexample, a Peltier device based on the Peltier effect.

In one or more embodiments, the switching element 110 is substantiallycoplanar with the first major surface 81 of the encapsulant 80. Thisensures good contact with the heatsink, which is necessary to maximizethe thermal efficiency.

In various embodiments, the first semiconductor chip 70 may be a powersemiconductor device, which may be a discrete device in one embodiment.In one embodiment, the first semiconductor chip 70 is a three terminaldevice such as a power metal insulator semiconductor field effecttransistor (MISFET), a junction field effect transistor (JFET), bipolarjunction transistor (BJT), an insulated gate bipolar transistor (IGBT),or a thyristor.

In various embodiments, the first semiconductor chip 70 may comprisepower chips, which, for example, draw large currents (e.g., greater than30 amperes). In various embodiments, the first semiconductor chip 70 isconfigured to operate at about 20 V to about 1000 V. In one embodiment,the first semiconductor chip 70 is configured to operate at about 20 Vto about 100 V. In one embodiment, the first semiconductor chip 70 isconfigured to operate at about 100 V to about 500 V. In one embodiment,the first semiconductor chip 70 is configured to operate at about 500 Vto about 1000 V. In various embodiments, the first semiconductor chip 70is configured to operate at about 10 V to about 10,000 V.

In one embodiment, the first semiconductor chip 70 is an n-channelMISFET. In another embodiment, the first semiconductor chip 70 is ap-channel MISFET. In one or more embodiments, the first semiconductorchip 70 may comprise a plurality of devices such as a vertical MISFETand a diode, or alternatively two MISFET devices separated by anisolation region.

The thickness of the first semiconductor chip 70 from the first side 61to the second side 62 may be less than 150 μm in various embodiments.The thickness of the first semiconductor chip 70 from the first side 61to the second side 62 may be less than 100 μm in various embodiments.The thickness of the first semiconductor chip 70 from the first side 61to the second side 62 may be less than 50 μm in various embodiments. Thethickness of the first semiconductor chip 70 from the first side 61 tothe second side 62 may be about 50 μm to about 150 μm in variousembodiments. The thickness of the first semiconductor chip 70 from thefirst side 61 to the second side 62 may be about 100 μm to about 150 μmin one embodiment. The thickness of the first semiconductor chip 70 fromthe first side 61 to the second side 62 may be about 50 μm to about 100μm in one embodiment.

Referring to FIG. 2C, the first semiconductor chip 70 is disposed over adie paddle of a leadframe 60. The second side 62 of the firstsemiconductor chip 70 includes a first contact region 71, a secondcontact region 72, and a third contact region 73. In one or moreembodiments, the first contact region 71 and the third contact region 73are coupled to a same region so as to form alternate contacts to thefirst semiconductor chip 70. For example, in one embodiment, the firstcontact region 71 and the third contact region 73 are both coupled to asame source region of a field effect transistor. In another embodiment,the first contact region 71 and the third contact region 73 are bothcoupled to a same emitter region of a transistor. In one or moreembodiments, the second contact region 72 is coupled to a gate of atransistor. In alternative embodiments, the second contact region 72 iscoupled to a base of a transistor.

A first interconnect 91 couples the second contact region 72, which iscoupled to a gate/base region, to a first gate/base lead 51. A secondinterconnect 92 couples the third contact region 73, which is coupled toa source/emitter region, to a first source/emitter lead 53. Because ofthe larger currents drawn through the first source/emitter lead 53, thesecond interconnect 92 may comprise a thicker wire relative to the firstinterconnect 91 in some embodiments. A first drain/collector lead 52 iscoupled to the first semiconductor chip 70 through the die paddle of theleadframe 60. Thus, in one embodiment, the semiconductor device 10 hasthe first gate/base lead 51, the first drain/collector lead 52, followedby the first source/emitter lead 53.

FIG. 2D illustrates a magnified cross-sectional view of the switchingelement 110 disposed under the leadframe 60. In one or more embodiments,the switching element 110 may comprise a diode. In one embodiment, theswitching element 110 comprises a semiconductor diode having a firstconductivity type region 111 and a second conductivity type region 112.The first conductivity type region 111 and the second conductivity typeregion 112 have opposite net doping so as to form a p/n junction.

FIG. 3, which includes FIGS. 3A-3D, illustrates schematics of electricalequivalent circuit diagram of semiconductor devices in accordance withembodiments of the invention.

Embodiments of the invention may be applied to any type of semiconductordevices. As example, embodiments of the invention may be applied topower devices, e.g., having vertical current flow. Due to the largecurrents flowing through these devices, they generate large amounts ofheat that need to be removed quickly to avoid heat buildup, which canimpact the performance of these devices negatively.

FIG. 3A illustrates an embodiment of the invention in which a switchingelement 110 is attached to a transistor 1. The transistor 1 has acontrol node G, a drain node D, and a source node S, which is coupled toa first potential node V1. As illustrated in one embodiment, theswitching element 110 is attached in series with the transistor 1. Afirst node of the switching element 110 is coupled to the drain node Dwhile a second node of the switching element 110 is coupled to anexternal potential node (second voltage node V2). During operation, apotential difference is maintained across the second node of theswitching element 110 and the source node S of the transistor 1.

In the ON state, the gate node is pulled up (assuming an n-channeltransistor), which renders the transistor 1 conducting. As thetransistor 1 begins to conduct, most of the potential difference betweenthe first voltage node V1 and the second voltage node V2 is appliedacross the switching element 110, which switches ON the switchingelement 110. Thus, when the heat is building up within the transistor 1(due to being in the ON state), the switching element 110 becomeselectrically conductive, which removes the thermal energy from thetransistor 1.

In one or more embodiments, the switching element 110 is configured toconduct when a positive potential difference above a threshold voltageis applied. In alternative embodiments, the switching element 110 isconfigured to conduct when a potential difference below a thresholdvoltage is applied. In one embodiment, the switching element 110 is adiode, which has low resistance to current flow in one direction whilehaving a large resistance in the opposite direction. Advantageously, thecurrent conduction also removes thermal energy from the transistor 1thereby cooling the transistor 1.

In the OFF state, the gate node is on low, which shuts OFF thetransistor 1. Thus, the potential difference between the first potentialnode V1 and the second potential node V2 is dropped mostly across thetransistor 1. As the potential difference across the first and thesecond terminals of the switching element 110 is below a thresholdvoltage, the switching element 110 stops to conduct current or stays inthe OFF state. Thus, in contrast to ON state, the switching element 110behaves as an isolation element in the OFF state, which thereforeisolates the heatsink from the transistor 1. Thus, the switching element110 behaves as an electro-thermal switch turning ON electrically andthermally (as a heat extractor) when the transistor 1 is in the ON stateand turning OFF electrically and thermally when the transistor 1 is inthe OFF state.

In various embodiments, the transistor 1 may comprise power metalinsulator semiconductor field effect transistors (MISFETs) or powerinsulated gate bipolar transistors (IGBTs). FIG. 3B illustrates anelectrical equivalent circuit diagram of a power MISFET while FIG. 3Cillustrates a power IGBT in accordance with embodiments of theinvention.

Such power MISFETs or power IGBTs may have varying dielectric strengthsdepending on the respective embodiment. For example, the dielectricstrengths may vary from a few 10 V up to a few 100V. The dielectricstrength is a maximum voltage across the source node to the drain node(the load path) that the transistor 1 is able to withstand withoutbreakdown in the OFF state. Power MISFETs and power IGBTs may ben-conducting and p-conducting transistors in various embodimentsalthough FIGS. 3B and 3C use circuit symbols for n-conductingtransistors.

In another embodiment as illustrated in FIG. 3D, the switching element110 may be attached differently. As illustrated, a first terminal of theswitching element 110 is attached to a drain of the transistor 1, whichis coupled to a second potential node V2. The second terminal of theswitching element 110 is coupled to a third potential node V3.

FIG. 4, which includes FIGS. 4A and 4B, illustrates cross-sectionalviews of the semiconductor device in accordance with embodiments of theinvention.

Referring to FIG. 4A, the switching element 110 may be formed under thefirst major surface 81 of the encapsulant 80. In one or moreembodiments, the switching element 110 may be attached to the leadframeusing a suitable conductive layer such as a conductive paste, solder,and others. Examples of the conductive paste may include metallicnano-paste, for example, comprising silver. In various embodiments, theadhesive conductive layer is applied uniformly over the entire exposedsurface of the leadframe 60 to ensure good thermal conduction.

FIG. 4B illustrates an alternative embodiment in which the leadframe 60is not directly coupled to the plurality of leads 50. Rather asdescribed in FIG. 3A, in some embodiments, the first semiconductor chip70 is coupled to an external voltage through the switching element 110.

FIG. 5, which includes FIGS. 5A and 5B, illustrates cross-sectionalviews of the semiconductor device in which the switching element isdisposed within the encapsulant in accordance with embodiments of theinvention.

FIGS. 5A and 5B illustrate embodiments in which the switching element110 covers the exposed bottom surface of the leadframe 60 but does notextend completely under the first major surface 81. Accordingly, in thisembodiment, the switching element 110 is disposed within the encapsulant80.

FIG. 6, which includes FIGS. 6A and 6B, illustrates cross-sectionalviews of the semiconductor device in which the switching element isdisposed within an auxiliary insulating layer in accordance withembodiments of the invention.

FIGS. 6A and 6B illustrate alternative embodiments in which theswitching element 110 is disposed within an insulating layer 120. Theinsulating layer 120 may be formed after forming the encapsulant 80 invarious embodiments. In various embodiments, the insulating layer 120may comprise a suitable dielectric material such as an oxide, nitride,or an encapsulant material.

FIG. 7, which includes FIGS. 7A and 7B, illustrates cross-sectionalviews of the semiconductor device in which the switching element isdisposed between a heatsink and the leadframe in accordance withembodiments of the invention.

FIGS. 7A and 7B illustrate embodiments of the invention in which aheatsink 150 is attached to the semiconductor device 10. The heatsink150 may be attached to the semiconductor device 10, for example, usingmounting screws through the opening 30.

FIG. 8, which includes FIGS. 8A and 8B, illustrates cross-sectionalviews of the semiconductor device in which the switching element isdisposed within the heatsink in accordance with embodiments of theinvention.

FIGS. 8A and 8B illustrate embodiments of the invention in which theswitching element 110 is formed within the heatsink 150. For example,the switching element 110 may be a part of a heatsink 150. In one ormore embodiments, the switching element 110 may be formed on a portionof a top surface of the heatsink 150. In alternative embodiments, theswitching element 110 may be formed on an entire top surface of theheatsink 150.

FIG. 9 illustrates a schematic circuit using embodiments of theinvention.

Embodiments of the invention may be used to form various types ofcircuits. Examples of such circuits include driver circuits such as halfbridge circuits and others used in regulating power including conversioncircuits. As but one example, a converter is illustrated using theswitching element described in various embodiments.

Referring to FIG. 9, a converter is formed as a boost converter andincludes a first semiconductor switching element 20, a secondsemiconductor switching element 30, a rectifier element 40 connected inparallel with the second semiconductor switching element 30, aninductive storage element 51, and a capacitive storage element 52. Theconverter has a first input terminal 11 and a second input terminal 12for applying an input voltage Vin and a first output terminal 13 and asecond output terminal 14 for providing an output voltage Vout. A loadmay be connected between the first and the second output terminals 13and 14.

Each of the first semiconductor switching element 20 and the secondsemiconductor switching element 30 respectively have a first load pathconnection 21, 31 and a second load path connection 22, 32 and a controlconnection 23, 33. A load path of the respective first and the secondswitching element 20 and 30 runs between the load path connections 21,31 and 22, 32, respectively. In n-conducting or n-channel devices, thefirst load path connections 21, 31 are drain connections and the secondload path connections 22, 32 are source connections. In p-conducting orp-channel devices, the first load path connections 21, 31 are sourceconnections and the second load path connections 22, 32 are drainconnections.

The rectifier element 40 has a first load path connection 41 and asecond load path connection 42, between which a load path is formed. Theload paths of the second semiconductor switching element 30 and of therectifier element 40 are connected in parallel with one another.

The first and the second semiconductor switching elements 20, 30 may bedriven to the ON state and to the OFF state according to drive signalsS20, S30, which are fed to the control connections 23, 33 of the firstand the second semiconductor switching elements 20, 30.

The input voltage Vin is less than the output voltage Vout for a boostconverter as illustrated in this example. The first semiconductorswitching element 20 controls a current by the inductive storage element51. For this purpose, the first semiconductor switching element 20 isconnected in series with the inductive storage element 51 between thefirst input terminal 11 and the second input terminal 12. A seriescircuit including the second semiconductor switching element 30 and thecapacitive storage element 52 is connected in parallel with the firstsemiconductor switching element 20. The rectifier element 40 isconnected with polarity such that it permits a current flow from theinductive storage element 51 to the capacitive storage element 52, butprevents such a current flow in the opposite direction.

As illustrated further in FIG. 9, the first semiconductor switchingelement 20 and the second semiconductor switching element 30 are coupledthrough corresponding a switching element 110 as discussed in variousembodiments above.

FIG. 10, which includes FIGS. 10A-10D, illustrates a semiconductordevice during various stages of fabrication in accordance with anembodiment of the invention.

Referring to FIG. 10A, a first semiconductor chip 70 is attached to aleadframe 60 having a plurality of leads 50. As next illustrated in FIG.10B, the switching element 110 is attached to the back side of theleadframe 60. In one or more embodiments, the switching element 110 maybe a semiconductor chip fabricated separately using a semiconductorwafer. However, in some embodiments, the switching element 110 may bedirectly deposited over the back side of the leadframe 60. As describedpreviously, the switching element 110 may be a semiconductor materialsuch as silicon, silicon germanium, silicon carbon, gallium nitride, andother materials. Alternatively, the switching element 110 may be formedusing organic semiconductor materials. In some embodiments, theswitching element 110 may also be formed using carbon such as carbonnanotubes, graphene, and others. The switching element 110 may beattached using any technique but ensures good thermal contact in variousembodiments. For example, a conductive layer/paste may be used in one ormore embodiments.

Referring next to FIG. 10C, after forming interconnects (e.g., wirebonds, clips, ribbons, strips, and others), the leadframe 60 with thefirst semiconductor chip 70 and the switching element 75 may be placedwithin a mold cavity of a molding tool 90.

In one or more embodiments, the encapsulating material is applied usinga compression molding process. In compression molding, the encapsulatingmaterial may be placed into a molding cavity, then the molding cavity isclosed to compress the encapsulating material. Compression molding maybe used when a single pattern is being molded.

As illustrated in FIG. 10C, the leadframe 60 with the firstsemiconductor chip 70 is placed within a molding tool 90 having a moldcavity. The encapsulating material may be introduced into the moldingtool 90, which may compress the encapsulant material in one embodiment.

In an alternative embodiment, the encapsulating material is appliedusing a transfer molding process. In other embodiments, theencapsulating material may be applied using injection molding, granulatemolding, powder molding, or liquid molding. Alternatively, theencapsulating material may be applied using printing processes such asstencil or screen printing.

In various embodiments, the encapsulanting material comprises adielectric material and may comprise a mold compound in one embodiment.In other embodiments, the encapsulanting material may comprise apolymer, a biopolymer, a fiber impregnated polymer (e.g., carbon orglass fibers in a resin), a particle filled polymer, and other organicmaterials. In one or more embodiments, the encapsulanting materialcomprises a sealant not formed using a mold compound, and materials suchas epoxy resins and/or silicones. In various embodiments, theencapsulanting material may be made of any appropriate duroplastic,thermoplastic, or thermosetting material, or a laminate. The material ofthe encapsulanting material may include filler materials in someembodiments. In one embodiment, the encapsulanting material may compriseepoxy material and a fill material comprising small particles of glassor other electrically insulating mineral filler materials like aluminaor organic fill materials.

The leadframe 60 is removed from the molding tool 90 and cured to formthe encapsulant 80 as illustrated in FIG. 10D. The encapsulatingmaterial deposited previously may be cured, i.e., subjected to a thermalprocess to harden so as to form a hermetic seal protecting thesemiconductor chip. The curing process hardens the encapsulatingmaterial thereby forming a single substrate comprising an encapsulant 80holding the leadframe 60 and the first semiconductor chip 70.

In some embodiments, the packaging may be performed using a batchprocess in which a plurality of first semiconductor chips 70 aresimultaneously packaged over a common leadframe 60 and formed within anencapsulant 80. Thus, a plurality of packages are formed which may besingulated to form a plurality of individual semiconductor devices 10.

FIG. 11, which includes FIGS. 11A-11C, illustrates a semiconductordevice during various stages of fabrication in accordance with anembodiment of the invention.

Unlike the previous embodiment illustrated in FIG. 10, in thisembodiment the semiconductor device 10 is fabricated using conventionalprocesses. After forming the semiconductor device 10, the leadframe 60is covered with a thin portion of the encapsulant 80 as illustrated inFIG. 11A.

Referring to FIG. 11B, the semiconductor device 10 is thinned from theback side so as to remove the thin portion of the encapsulant 80. In oneor more embodiments, the thinning may be performed chemically,mechanically, or chemical-mechanically.

The switching element 110 is formed on the exposed leadframe 60 asillustrated in FIG. 11C. For example, the switching element 110 may beformed separately and may be attached to the exposed surface of thesemiconductor device 10.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. As an illustration, the embodiments described in FIG. 2 maybe combined with the embodiments described in FIGS. 4-9. It is thereforeintended that the appended claims encompass any such modifications orembodiments.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. For example,it will be readily understood by those skilled in the art that many ofthe features, functions, processes, and materials described herein maybe varied while remaining within the scope of the present invention.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

What is claimed is:
 1. A semiconductor module comprising: a leadframehaving a first side and an opposite second side; a semiconductor chipdisposed over the first side of the leadframe; and a switching elementdisposed under the second side of the leadframe, wherein the switchingelement has a first surface facing the leadframe and an opposite secondsurface for mounting a heatsink, wherein the switching element isconfigured to electrically isolate the semiconductor chip from theheatsink when the semiconductor chip is active and electrically couplethe semiconductor chip with the heatsink when the semiconductor chip isnot active.
 2. The semiconductor module according to claim 1, whereinthe semiconductor chip comprises a contact region coupled to an externalpotential node through a lead of the leadframe.
 3. The semiconductormodule according to claim 1, wherein the semiconductor chip comprises acontact region coupled to an external potential node through theswitching element.
 4. The semiconductor module according to claim 1,wherein the switching element comprises a diode.
 5. The semiconductormodule according to claim 4, wherein the diode comprises a semiconductordiode.
 6. The semiconductor module according to claim 5, wherein thesemiconductor diode comprises silicon.
 7. The semiconductor moduleaccording to claim 4, wherein the diode comprises a carbon basedsemiconductor.
 8. The semiconductor module according to claim 1, furthercomprising an encapsulant disposed at the leadframe.
 9. Thesemiconductor module according to claim 8, wherein the switching elementis disposed within the encapsulant.
 10. The semiconductor moduleaccording to claim 1, wherein the leadframe comprises a die paddle overwhich the semiconductor chip is disposed, wherein the die paddle has afirst footprint and the switching element has a second footprint,wherein the first footprint is about the same as the second footprint.11. The semiconductor module according to claim 1, further comprising aheatsink disposed under the switching element.
 12. The semiconductormodule according to claim 11, wherein the switching element is disposedwithin the heatsink.
 13. The semiconductor module according to claim 12,wherein the semiconductor chip comprises a source/emitter region and adrain/collector region, wherein the drain/collector region iselectrically coupled to a first terminal of the switching element, andwherein a second terminal of the switching element is electricallycoupled to the heatsink.
 14. A semiconductor module comprising: a firstdiscrete semiconductor device including a first lead and a second lead;and a first switching element having a first terminal and a secondterminal, the first terminal of the first switching element electricallyand thermally coupled to the first discrete semiconductor device, thefirst switching element configured to conduct heat away from the firstdiscrete semiconductor device, wherein the first switching element isconfigured to electrically isolate the first discrete semiconductordevice from a heatsink disposed below the first switching element whenthe first discrete semiconductor device is not active, wherein the firstswitching element is configured to electrically and thermally couple thefirst discrete semiconductor device to the heatsink when the firstdiscrete semiconductor device is active.
 15. The semiconductor moduleaccording to claim 14, wherein the first lead is a source/emitter lead,and wherein the second lead is a drain/collector lead.
 16. Thesemiconductor module according to claim 14, wherein the first switchingelement comprises a discrete diode.
 17. The semiconductor moduleaccording to claim 14, further comprising a second discretesemiconductor device including a third lead and a fourth lead, thesecond lead and the fourth lead being coupled to a first potential node,wherein the second lead is coupled to the first potential node throughthe first switching element.
 18. The semiconductor module according toclaim 17, wherein the first lead is a first source/emitter lead, whereinthe second lead is a first drain/collector lead, wherein the third leadis second source/emitter lead, and wherein the fourth lead is a seconddrain/collector lead.
 19. The semiconductor module according to claim17, further comprising a second switching element having a firstterminal and a second terminal, the first terminal of the secondswitching element being coupled to the fourth lead.
 20. Thesemiconductor module according to claim 17, wherein the first discretesemiconductor device comprises a discrete insulated gate bipolartransistor, and wherein the second discrete semiconductor device alsocomprises a discrete insulated gate bipolar transistor.
 21. Thesemiconductor module according to claim 17, wherein the first discretesemiconductor device comprises a discrete metal insulator field effecttransistor, and wherein the second discrete semiconductor device alsocomprises a discrete metal insulator field effect transistor.
 22. Amethod of forming a semiconductor module, the method comprising:providing a semiconductor device comprising a leadframe having a firstside and an opposite second side and a semiconductor chip disposed overthe first side of the leadframe; and attaching a switching element atthe second side of the leadframe, wherein the switching element has afirst surface facing the leadframe and an opposite second surface formounting a heatsink, wherein the switching element is configured toelectrically isolate the semiconductor chip from the heatsink when thesemiconductor chip is active and electrically couple the semiconductorchip with the heatsink when the semiconductor chip is not active. 23.The method according to claim 22, wherein the switching elementcomprises a semiconductor diode.
 24. The method according to claim 22,wherein attaching the switching element comprises attaching asemiconductor diode under the second side of the leadframe.
 25. Themethod according to claim 22, wherein attaching the switching elementcomprises forming a carbon based material under the second side of theleadframe.
 26. The method according to claim 22, further comprisingattaching a heatsink to the switching element.
 27. The method accordingto claim 22, wherein attaching the switching element comprises attachinga heatsink, and wherein the switching element is disposed within theheatsink.
 28. A semiconductor module comprising: a discrete verticaltransistor including a first transistor terminal and a second transistorterminal; a discrete diode having a first terminal and a secondterminal; and a die paddle having a first side and an opposite secondside, wherein the discrete vertical transistor is mounted on the firstside of the die paddle, and wherein the discrete diode is mounted on thesecond side of the die paddle, wherein the first transistor terminal iselectrically and thermally coupled to the first terminal through the diepaddle, wherein the discrete diode is configured to be in an ON statewhen the discrete vertical transistor is operating at an ON state andthe discrete diode is configured to be in an OFF state when the discretevertical transistor is operating at an OFF state.
 29. The semiconductormodule according to claim 28, further comprising: an encapsulantdisposed over the discrete vertical transistor and the die paddle; andan insulating layer disposed over the encapsulant, wherein the discretediode is disposed within the insulating layer.
 30. The semiconductormodule according to claim 28, further comprising: an encapsulantdisposed over the discrete vertical transistor, the discrete diode, andthe die paddle, wherein the discrete diode is disposed within theencapsulant, wherein the die paddle has a first footprint and thediscrete diode has a second footprint, wherein the first footprint isless than the second footprint.